# verilog和systemverilog通用部分

snippet co      "comment always block"
/*-------------------------------------------------------------------------
//description   : ${1}
//parameter     :
//others        :
-------------------------------------------------------------------------*/
endsnippet

#module`!v strftime("%Y-%m-%d")`
#module ${1:/*module*/}
snippet mo      "modele without parameter"
\`timescale  1 ns/1 ps

module ${1:name}
(
    input                       clk,
    input                       rst,
    ${2:/*port*/}
);

endmodule
endsnippet

#module ${1:/*module*/} #
snippet mod  "modele with parameter"
module ${1:name} #
(
    ${2:/*parameter*/}
)
(
    input                       clk,
    input                       rst,
    ${3:/*port*/}
);

endmodule
endsnippet

snippet if "if...begin...end"
if(${1:/*condition*/})
begin
    ${2:/*code*/}
end
endsnippet

snippet el "else...begin...end"
else
begin
    ${1:/*code*/}
end
endsnippet

snippet elif "else if...begin...end"
else if(${1:/*condition*/})
begin
    ${2:/*code*/}
end
endsnippet

snippet assign  "assign ..."
assign                  ${1:LHS} = ${2:RHS};
endsnippet

snippet paramter  "paramter ..."
parameter               ${1:LHS} = ${2:RHS};
endsnippet

snippet localparam  "localparam ..."
localparam              ${1:LHS} = ${2:RHS};
endsnippet

snippet tri   "inout port in testbench"
tri [${1:data_width}:00] ${1:nand_data} = $1'bz;
assign (weak1, weak0) $2 = 0;
endsnippet

snippet inout   "inout port template"
assign                  ${1:inout_port} = ${2:enable} ? ${3:data_out} : 16'hzzzz ;
assign                  ${4:data_in} = $1;
//$2 = 1时，输出$3; $2 = 1, 端口设置为高阻，当做输入端口
//$4为外部输入的数据
endsnippet

snippet edge "detect edge"
reg    [1:0]            ${1:Reg}_r = 2'b00;
wire                    $1_rise;
wire                    $1_fall;

assign          $1_rise = $1_r[1:0] == 2'b01;
assign          $1_fall = $1_r[1:0] == 2'b10;
always @ (posedge clk)
begin
	$1_r    <= {$1_r[0], $1};
end
endsnippet

snippet ini     "initial ... begin ... end"
initial
begin
    ${1:/*code*/}
end
endsnippet

#case
snippet ca      "case ... endcase"
case (${1:/*condition*/})
${2:/*first*/}:
begin
    ${3:/*code*/}
end
${4:/*code*/}
default:
begin
    ${5:/*code*/}
end
endcase
endsnippet

snippet ?
${1:/*LHS*/} = ${2:/*condition*/} ? ${3:/*expr1*/} : ${4:/*expr2*/};
endsnippet

snippet be  "beging...end"
begin
    ${1:/*code*/}
end
endsnippet

snippet for     "for loop"
for(int i = 0; i < ${1:num}; i = i + 1 )
begin
    ${2:/*code*/}
end
endsnippet

snippet ifdef "compiler directives" b
\`ifdef ${1:MACRO}
    //do
\`elsif ${2:MACRO}
    //do
\`else
    //do
\`endif
endsnippet

snippet `d
\`define          DELAY   1

endsnippet

snippet pipe "pipeline data"
reg     [17:00]             ${1:data_in}_r0;
reg     [17:00]             $1_r1;

always @ (posedge clk)
begin
    $1_r0 <= $1;
    $1_r1 <= $1_r0;
end
endsnippet

snippet clogb2  "return log2(b)"
/* 
 * 2^x = bit_depth, return x
 */
function integer clogb2 (input integer size);
    begin
      size = size - 1;
      for (clogb2=1; size>1; clogb2=clogb2+1)
        size = size >> 1;
    end
  endfunction // clogb2
endsnippet


snippet ibufds "xilinx input buffer differential signal" b
IBUFDS #
(
    .DIFF_TERM       (  "FALSE"      ),       // Differential Termination
    .IBUF_LOW_PWR    (  "TRUE"       ),     // Low power="TRUE", Highest performance="FALSE"
    .IOSTANDARD      (  "DEFAULT"    )
) 
IBUFDS_inst
(
    .O               (  O            ),  // Buffer output
    .I               (  I            ),  // Diff_p buffer input
    .IB              (  IB           )// Diff_n buffer input
);
endsnippet

snippet shift_in_high   "first data in high"
${1:new_data}[7:0] <= {$1[${2:6}:${3:0}], ${4:data_in}};             // 最先进来的数据在最高位
endsnippet

snippet shift_in_low   "first in in low"
${1:new_data}[7:0] <= {${3:data_in}, $1[${2:7}:${4:1}]};             // 最先进来的数据在最低位
endsnippet

snippet shift_out_high   "High bit first go out"
/* 需要其他地方不断给 data_in_reg 赋值，例如
if(load)
    ${1:data_in_reg} <= data_in
else
*/
begin
    $1 <= ($1 << 8);
    ${2:data_out} <= $1[31:24]
end
endsnippet

snippet shift_out_low   "low bit first go out"
/* 需要其他地方不断给 data_in_reg 赋值，例如
if(load)
    ${1:data_in_reg} <= data_in
else
*/
begin
    $1 <= ($1 >> 8);
    ${2:data_out} <= $1[07:00]
end
endsnippet

snippet ila "ila instantiation"
ila_0 ila_0Ex01
(
    .clk       (  clk ),
    .probe0    (      )
);
endsnippet

snippet vio "vio instantiation"
vio_0 vio_0Ex01
(
    .clk			(  clk ),
    .probe_out0     (      )
);
endsnippet

snippet sys_reset "proc sys reset"
proc_sys_reset_0 proc_sys_reset_0
(
    .slowest_sync_clk        (  ${1:clk_125m}                          ),
    .ext_reset_in            (  1'b0                              ),
    .aux_reset_in            (  1'b0                              ),
    .mb_debug_sys_rst        (  1'b0                              ),
    .dcm_locked              (  dcm_locked                        ),
    .mb_reset                (                                    ),
    .bus_struct_reset        (                                    ),
    .peripheral_reset        (  ${2:rst_125m}                          ),
    .interconnect_aresetn    (                                    ),
    .peripheral_aresetn      (                                    )
);
endsnippet
